1. Field of the Invention
The present invention relates to methods for programming and reading a NAND flash memory device and a page buffer performing the same, and more particularly, to methods for programming and reading a multi-level-cell NAND flash memory device and a page buffer performing the same.
2. Description of the Related Art
In a traditional NAND flash memory device, memory cells can take one of two information storing states, namely, the “ON” state and the “OFF” state. One bit of information is defined by the ON or OFF state of a respective memory cell. In order to store data of N bits (N: a positive integer of 2 or greater) in the aforesaid traditional NAND flash memory device, N independent memory cells are necessary. When it is required to increase the number of bits of data to be stored in a NAND flash memory device having one-bit memory cells, the number of such memory cells should increase accordingly. Information stored in the one-bit memory cell is determined by the programmed status of the memory cell where programming is used to store the desired information in the memory cell. The information storing state of the memory cell is determined by the threshold voltage which is a minimum voltage to be applied between the gate and source terminals of the transistor included in the memory cell to switch the cell transistor to its ON state.
To increase the storage capacity without increasing the number of memory cells, information stored in the memory cell can be increased to more than two states in one memory cell, instead of the above mentioned “ON-OFF, two state” memory cell. Such a multi-level cell stores more than one bit information. The most commonly used such memory cell has 2 bits of information in one memory cell, in which 4 distinctly different states need to be defined, normally by the threshold voltage definition described as follows.
FIG. 1 shows a threshold voltage distribution of a memory cell according to programmed data, in which the programmed data exhibits one of a threshold voltage (indicating 2-bit data of (11)) lower than −2.0V, a threshold voltage (indicating 2-bit data of (10)) between 0.3V to 0.7V, a threshold voltage (indicating 2-bit data of (01)) between 1.3V to 1.7V, and a threshold voltage (indicating 2-bit data of (00)) between 2.3V to 2.7V. Data can be stored in four different states in one memory cell on the basis of such threshold voltage distributions.
FIG. 2 shows two strings in a memory cell array 20 of a NAND flash memory device, where each memory cell 10 stores two-bit information. The memory cell array 20 comprises plural memory cells 10 connected in series between a bit line (BL1 or BL2) and a ground select line GSL. A group of memory cells 10 connected in series to one bit line (BL1 or BL2) along with select transistors (a string select transistor SST and a ground select transistor GST) used to select the memory cells 10 is called a string. The string select transistor SST is selectively switched on to couple the associated string and the bit line together. The ground select transistor GST is selectively switched the connection between each string and a common source line CSL.
As for the program operation and the read operation applied in a multi-level-cell NAND flash memory device, some traditional program methods are given as follows. U.S. Pat. No. 2005/0018488, herein incorporated by reference and hereinafter '488, discloses a method to program the memory cell with two pages of data. One page of data is programmed to the LSBs (least significant bit) of the memory cells and another page of data is programmed to the MSBs (most significant bit) of the memory cells. FIG. 3 shows the state transition of the memory cells of the program operation in '488. Referring to FIG. 3, the LSBs of the memory cells are programmed first from the (11) state to the (11) state, or to the (10) state as indicated by a pointer A, in a page program. Then, the MSBs of the memory cells are programmed in another page program. In the MSB program, the memory cells in the (11) state will be programmed to the (11) state, or to the (01) state as indicated by a pointer B1, and the memory cells in the (10) state will be programmed to the (00) state as indicated by a pointer B2. The B1 and B2 MSB programs occur simultaneously. The bit line voltage level is 0V for the B1 MSB program; however, the B2 MSB program is slowed down by tuning the bit line voltage level between 0V and a source voltage (e.g. Vcc) to fit the programming time of the B1 MSB program. A method to read the memory cells is disclosed in '488, which includes a two-phase LSB read and a one-phase MSB read. The two-phase LSB read comprises the LSB1 read and the LSB2 read. The voltages Vrd3, Vrd1, and Vrd2 are applied to the selected word line in the LSB1 read, the LSB2 read, and the MSB read, respectively. Note that the relation of Vrd3>Vrd2>Vrd1 exists, as shown in FIG. 3.
U.S. Pat. No. 6,937,510, herein incorporated by reference and hereinafter '510, discloses a method to program the memory cell with two pages of data. Referring to FIG. 4, a memory cell has four possible levels, (0), (1), (2), and (3), which shows the state transition of the memory cells of the program operation in '510. The threshold voltage distribution of FIG. 4 is similar to that of FIG. 3. In FIG. 4, the LSBs of the memory cells are programmed from the (0) state to the (0) state, or to the (1) state as indicated by a pointer C, in a page program. Then, the MSBs of the memory cells are programmed in another page program. In the MSB program, the memory cells in the (0) state are programmed to the (0) state, or to the (2) state as indicated by a pointer D1, and the memory cells in the (1) state will be programmed to the (1) state, or to the (3) state as indicated by a pointer D2. The D1 and D2 MSB programs occur simultaneously. The bit line voltage level is 0V for the D2 MSB program; however, the D1 MSB program is slowed down by tuning the bit line voltage level between 0V and a source voltage (e.g. Vcc) to fit the programming time of the D2 MSB program. A method to read the memory cells is disclosed in '510, which employs a three-phase read to distinguish the four levels of (0), (1), (2), and (3) with the voltages of Vrd3, Vrd2, and Vrd1 applied to the selected word line, respectively. Note that the relation of Vrd3>Vrd2>Vrd1 exists, as shown in FIG. 4.